Creating Assertion-Based IP [Paperback]

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions

Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning and is the first book published on this subject.

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the users existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:

• modularityassertion-based IP should have a clear separation between detection and action
  
  
• clarityassertion-based IP should be writtenl3Ä