Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS [Hardcover]

This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. 

Chapter 1. Introduction.- Chapter 2. State of the Art.- Chapter 3. Modeling Cell-internal EM.- Chapter 4. Current Calculation.- Chapter 5. Experimental Setup.- Chapter 6.Results.- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers.- Chapter 8. Conclusions.

Gracieli Posser is a post-doctoral researcher at Universidade Federal do Rio Grande do Sul (UFRGS) and Inter-Software Engineer at Cadence Design Systems - Austin, TX.

Sachin S. Sapatnekar holds the Distinguished McKnight University Professorship and the Robert and Marjorie Henle Chair in Electrical and Computer Engineering at the University of Minnesota. He has authored nine books and numerous papers in this area and has received six conference Best Paper Awards and a Best Poster Award, as well as the ICCAD Ten-Year Retrospective Most Influential Paper Award, an award that recognizes a paper that has had a significant impact ten years after its publication.  lÓ4