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Field Programmable Logic and Applications: 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. [Paperback]

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  • Category: Books (Computers)
  • ISBN-10:  3540634657
  • ISBN-10:  3540634657
  • ISBN-13:  9783540634652
  • ISBN-13:  9783540634652
  • Publisher:  Springer
  • Publisher:  Springer
  • Pages:  512
  • Pages:  512
  • Binding:  Paperback
  • Binding:  Paperback
  • Pub Date:  01-Feb-1997
  • Pub Date:  01-Feb-1997
  • SKU:  3540634657-11-SPRI
  • SKU:  3540634657-11-SPRI
  • Item ID: 105251901
  • List Price: $54.99
  • Seller: ShopSpell
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This book constitutes the refereed proceedings of the 7th International Workshop on Field Programmable Logic and Applications, FPL '97, held in London, UK, in September 1997. The 51 revised full papers in the volume were carefully selected from a large number of high-quality papers. The book is divided into sections on devices and architectures, devices and systems, reconfiguration, design tools, custom computing and codesign, signal processing, image and video processing, sensors and graphics, color and robotics, and applications.Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor.- CAD-oriented FPGA and dedicated CAD system for telecommunications.- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools.- Extending dynamic circuit switching to meet the challenges of new FPGA architectures.- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs.- Implementation of pipelined multipliers on Xilinx FPGAs.- The XC620ODS development system.- Thermal monitoring on FPGAs using ring-oscillators.- A reconfigurable approach to low cost media processing.- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research.- Stream synthesis for a wormhole run-time reconfigurable platform.- Pipeline morphing and virtual pipelines.- Parallel graph colouring using FPGAs.- Run-time compaction of FPGA designs.- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement.- A case study of partially evaluated hardware circuits: Key-specific DES.- Run-time parameterised circuits for the Xilinx XC6200.- Automatic identification of swappable logic units in XC6200 circuitry.- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic.- Exploiting reconfigurability through domain-specific systems.- Technology mapping by binate covering.-l#[
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