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Digital System Test and Testable Design: Using HDL Models and Architectures [Hardcover]

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  • Category: Books (Technology & Engineering)
  • Author:  Navabi, Zainalabedin
  • Author:  Navabi, Zainalabedin
  • ISBN-10:  1441975470
  • ISBN-10:  1441975470
  • ISBN-13:  9781441975478
  • ISBN-13:  9781441975478
  • Publisher:  Springer
  • Publisher:  Springer
  • Pages:  490
  • Pages:  490
  • Binding:  Hardcover
  • Binding:  Hardcover
  • Pub Date:  01-Mar-2010
  • Pub Date:  01-Mar-2010
  • SKU:  1441975470-11-SPRI
  • SKU:  1441975470-11-SPRI
  • Item ID: 100183763
  • List Price: $119.99
  • Seller: ShopSpell
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  • Delivery by: Sep 29 to Oct 01
  • Notes: Brand New Book. Order Now.
This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.About the AuthorDr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabis involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL couló*
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