Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs [Paperback]

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Introduction.-Reconfigurable Real-Time Memory Controller Architecture.- Memory Patterns.- Cycle-AccurateSDRAM Power Modeling.- Power/Performance Trade-Offs.- Conservative Open-PagePolicy.- Reconfiguration.- Related Work.- Conclusions and Future Work.- Appendix A: ILP Problem Formation.- AppendixB: Memory Specifications.- Appendix C: Code Listings.- Appendix D: List ofAcronyms.- Appendix E: List of Symbols.

Sven Goossens receivedhis M.Sc. in Embedded Systems from the Eindhoven University of Technology in2010. He worked as a researcher in the Electrical Engineering of the sameuniversity until 2011, and then started as a Ph.D. student, graduating in 2015.He is currently employed as a Hardware Architect at Intrinsic-ID. His researchinterests include mixed time-criticality systems, composability and SDRAMcontrollers.

Karthik Chandrasekar earnedhis M.Sc. degree in Computer Engineering from TU Delft in the Netherlands inNovember 2009. In October 2014, he received his Ph.D. also from the sameuniversity. His research interests include SoC Architectures,DRAM memories & memory controllers, on-chip communication networks andperformance & power modeling and analysis. He is currently employed as aSenior Architect at Nvidia.