On and Off-Chip Crosstalk Avoidance in VLSI Design [Hardcover]

Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk, which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design.

This book focuses on crosstalk avoidance with bus encoding, one of the techniques that selectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption.

On-Chip Crosstalk and Avoidance.- of On-Chip Crosstalk Avoidance.- Preliminaries to On-chip Crosstalk.- Memoryless Crosstalk Avoidance Codes.- CODEC Designs for Memoryless Crosstalk Avoidance Codes.- Memory-based Crosstalk Avoidance Codes.- Multi-valued Logic Crosstalk Avoidance Codes.- Summary of On-Chip Crosstalk Avoidance.- Off-Chip Crosstalk and Avoidance.- to Off-Chip Crosstalk.- Package Construction and Electrical Modeling.- Preliminaries and Terminology.- Analytical Model for Off-Chip Bus Performance.- Optimal Bus Sizing.- Bus Expansion Encoder.- Bus Stuttering Encoder.- Impedance Compensation.- Future Trends and Applications.- Summary of Off-Chip Crosstalk Avoidance.

On- and Off-Chip Crosstalk Avoidance in VLSI Design

Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri

Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip datlsb