Stress and Strain Engineering at Nanoscale in Semiconductor Devices [Paperback]

Chapter 1. Introduction

Chapter 2. Simulation Environment

Chapter 3. Stress Generation Techniques in CMOS Technology

Chapter 4. Electronic Properties of Engineered Substrates

Chapter 5. Bulk-Si FinFETs

Chapter 6. Strain-Engineered FinFETs at NanoScale

Chapter 7. Technology CAD of III-Nitride Based Devices

Chapter 8. Strain-Engineered SiGe Channel TFT for Flexible Electronics

Based on 3D process and device simulations with mechanical stress simulations by finite element techniques, this book explains performance assessment of nanoscale devices with strained SiGe and other stressors. It explains the process-induced stress transfer and developments at 7nm technology and below node in the area of strain-engineered devices.

Anticipating a limit to the continuous miniaturization (More-Moore), intense research efforts are being made to co-integrate various functionalities (More-than-Moore) in a single chip. Currently, strain engineering is the main technique used to enhance the performance of advanced semiconductor devices. Written from an engineering applications standpoint, this book encompasses broad areas of semiconductor devices involving the design, simulation, and analysis of Si, heterostructure silicongermanium (SiGe), and III-N compound semiconductor devices. The book provides the background and physical insight needed to understand the new and future developments in the technology CAD (TCAD) design at the nanoscale.

Features

• Covers stressstrain engineering in semiconductor devices, such as FinFETs and III-V Nitride-based devices
• Includes comprehensive mobility model for strained substrates in global and local strain techniques and their implementation iló/