Vertical 3D Memory Technologies [Hardcover]

The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and double gate memories,  terrabit vertical channel and vertical gate stacked NAND flash, large scale stacking of  Resistance RAM cross-point arrays, and 2.5D/3D stacking of memory and processor chips with through-silicon-via  connections now and remote links later.

Key features:

• Presents a review of the status and trends in 3-dimensional vertical memory chip technologies.
• Extensively reviews advanced vertical memory chip technology and development
• Explores technology process routes and 3D chip integration in a single reference

1 Basic Memory Device Trends Toward the Vertical 1

1.1 Overview of 3D Vertical Memory Book 1

1.2 Moore’s Law and Scaling 2

1.3 Early RAM 3D Memory 3

1.3.1 SRAM as the First 3D Memory 3

1.3.2 An Early 3D Memory—The FinFET SRAM 6

1.3.3 Early Progress in 3D DRAM Trench and Stack Capacitors 6

1.3.4 3D as the Next Step for Embedded RAM 11

1.4 Early Nonvolatile Memories Evolve to 3D 13

1.4.1 NOR Flash Memory—Both Standalone and Embedded 13

1.4.2 The Charge-Trlˆ