This book explains how to specify, design, and test a complete digital system using Verilog.This book describes how to specify, design, and test a complete digital system using Verilog, a leading commercial hardware description language. After a brief introduction to the Verilog language, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. This ISA is used throughout the remainder of the book to demonstrate how both behavioral and structural models can be developed and intermingled in Verilog. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practicing engineers.This book describes how to specify, design, and test a complete digital system using Verilog, a leading commercial hardware description language. After a brief introduction to the Verilog language, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. This ISA is used throughout the remainder of the book to demonstrate how both behavioral and structural models can be developed and intermingled in Verilog. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practicing engineers.Using Verilog, a leading commercial hardware description language, this text describes how to specify, design, and test a complete digital system. After a brief introduction to the Verilog language, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. The remainder of the book demonstrates how both behavioral and structural models can be developed and intermingled in Verilog.Preface; 1. Controlling complexity; 2. A verilogical place to start; 3. Defining the instruction set architecture; 4. Algorithmic behavioral modeling; 5. Building an assembler for VeSPA; 6. Pipelining; 7. Implementation of the pipelined processor; 8. Verification; Appendix A: the Vels+