Designing Reliable and Efficient Networks on Chips [Hardcover]

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

The book provides state-of-the-art methods to solve some of the most important problems encountered during NoC design. It is the first book to present in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs.

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

Preface. 1 Introduction. 1.1 Networks on Chips: Scalable interconnects for SoCs. 1.2 NoC Design Challenges. 1.3 Book Overview. 1.4 Related Work. Part I NoC Design Methods 2 Designing Crossbar Based Systems. 2.1 Problem Motivation and Application Traffic Analysis. 2.2 Design Methodology. 2.3 Exact Approach to Crossbar Synthesis. 2.4 Heuristic Aplc-