Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology.
Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology. Topics include: an extensive review of Moore's Law, the classical regime for SiO2 gate dielectrics; the transition to silicon oxynitride gate dielectrics; the transition to high-K gate dielectrics (including the drive towards equivalent oxide thickness in the single-digit nanometer regime); and future directions and issues for ultimate technology generation scaling. The vision, wisdom, and experience of the team of authors will make this book a timely, relevant, and interesting, resource focusing on fundamentals of the 45 nm Technology Generation and beyond.
Classical Regime for SiO.- Brief Notes on the History of Gate Dielectrics in MOS Devices.- SiO2 Based MOSFETS: Film Growth and SiSiO2 Interface Properties.- Oxide Reliability Issues.- The Economic Implications of Moore's Law.- Transition to Silicon Oxynitrides.- Gate Dielectric Scaling to 2.01.0 nm: SiO2 and Silicon Oxynitride.- Optimal Scaling Methodologies and Transistor Performance.- Silicon Oxynitride Gate Dielectric for Reducing Gate Leakage and Boron Penetration Prior to High-k Gate Dielectrl“-