Power Distribution Networks with On-Chip Decoupling Capacitors [Paperback]

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems.

Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

With more than 100 pages of new content, this updated edition provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors.

Introduction.- Inductive Properties of Electric Circuits.- Properties of On-Chip Inductive Current Loops.- Electromigration.- Scaling Trends of On-Chip Power Distribution Noise.- High Performance Power Distribution Systems.- On-Chip Power Distribution Networks.- Computer-Aided Design and Analysis.- Closed Form Expressions for Fast IR Drop Analysis.- Inductive Properties of On-Chip Power Distribution Grids.- Variation of Grid Inductance with Frequency.- Inductance/Area/Resistance Tradeoffs Inductance Model of Interdigitated Power and Ground Distribution Networks.- On-chip Power Noise Reduction Techniques in High Performance ICs.- Impedance/Noise Issues in On-Chip Power Dl3t