Logic Synthesis for FSM-Based Control Units [Hardcover]

This book presents the hardware implementation of control algorithms represented by graph-schemes of algorithm. It includes new methods of logic synthesis and optimization for logic circuits of Mealy and Moore FSMs oriented on both ASIC and FPLD.

Hardwired Interpretation of Control Algorithms.- Matrix Realization of Control Units.- Evolution of Programmable Logic.- Optimization for Logic Circuit of Mealy FSM.- Optimization for Logic Circuit of Moore FSM.- FSM Synthesis with Transformation of GSA.- FSM Synthesis with Object Code Transformation.- FSM Synthesis with Elementary Chains.- Conclusion.

The control unit is one of the most important parts of any digital system responsible for interplay of other system blocks. Very often, the model of a finite state machine (FSM) is used to represent the behaviour of a control unit. Modern computer-aided design tools include a lot of optimal solutions (library cells) for implementation of such regular blocks of digital systems as decoders, multiplexers, parallel multibit adders and so on. But as a rule, control units have an irregular structure which makes impossible to design their logic circuits using the standard library cells. To use these cells, an FSM can be represented by a multilevel model based on the principle of structural decomposition. In multilevel models, for example, multiplexers are used to replace logical conditions, decoders are used to implement microoperations, and different memory blocks are used to transform object codes.

Design methods depend strongly on such factors as an FSM model in use, specific features of logic elements implementing its logic circuit, characteristics of a control algorithm to be interpreted. In the case of Moore FSM, optimization methods are based on existence of the classes of pseudoequivalent states. Their use permits to compress the transition table of Moore FSM till the size of the table for equivalent Mealy FSM. In the case of Meallóá