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Microprocessor Architecture From Simple Pipelines to Chip Multiprocessors [Hardcover]

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  • Category: Books (Computers)
  • Author:  Baer, Jean-Loup
  • Author:  Baer, Jean-Loup
  • ISBN-10:  0521769922
  • ISBN-10:  0521769922
  • ISBN-13:  9780521769921
  • ISBN-13:  9780521769921
  • Publisher:  Cambridge University Press
  • Publisher:  Cambridge University Press
  • Pages:  382
  • Pages:  382
  • Binding:  Hardcover
  • Binding:  Hardcover
  • Pub Date:  01-May-2009
  • Pub Date:  01-May-2009
  • SKU:  0521769922-11-MPOD
  • SKU:  0521769922-11-MPOD
  • Item ID: 100228714
  • Seller: ShopSpell
  • Ships in: 2 business days
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  • Delivery by: Jun 30 to Jul 02
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This book describes the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars.This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as  the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers  optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations  design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors  state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how thlcl
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