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Cutting-Edge CMOS VLSI Design for Manufacturability Techniques
This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes,Nanoscale CMOS VLSI Circuits: Design for Manufacturabilityfocuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource.
Nanoscale CMOS VLSI Circuitscovers:
- Current trends in CMOS VLSI design
- Semiconductor manufacturing technologies
- Photolithography
- Process and device variability: analyses and modeling
- Manufacturing-Aware Physical Design Closure
- Metrology, manufacturing defects, and defect extraction
- Defect impact modeling and yield improvement techniques
- Physical design and reliability
- DFM tools and methodologies
Chapter 1.Introduction;
Chapter 2.Semiconductor Manufacturing;
Chapter 3.Process and Device Variability: Analysis and Modeling;
Chapter 4.Manufacturing-Aware Physical Design Closure;
Chapter 5.Metrology, Manufacturing Defects, and Defect Extraction;
Chapter 6.Defect Impact Modeling and Yield Improvement Techniques;
Chapter 7.Physical Design and Reliability;
Chapter 8.Design for Manufacturability: Tools and Methodologies
Dr. Sandip Kunduis a professor in the Electrical and Computer Engineering Department at the University of Massachusetts at Amherst, specializing in semiconductor and lithographic manufacturing.
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