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Network-on-Chip Architectures A Holistic Design Exploration [Hardcover]

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  • Category: Books (Technology & Engineering)
  • Author:  Nicopoulos, Chrysostomos, Narayanan, Vijaykrishnan, Das, Chita R.
  • Author:  Nicopoulos, Chrysostomos, Narayanan, Vijaykrishnan, Das, Chita R.
  • ISBN-10:  9048130301
  • ISBN-10:  9048130301
  • ISBN-13:  9789048130306
  • ISBN-13:  9789048130306
  • Publisher:  Springer
  • Publisher:  Springer
  • Pages:  223
  • Pages:  223
  • Binding:  Hardcover
  • Binding:  Hardcover
  • Pub Date:  01-Feb-2009
  • Pub Date:  01-Feb-2009
  • SKU:  9048130301-11-SPRI
  • SKU:  9048130301-11-SPRI
  • Item ID: 100980483
  • List Price: $169.99
  • Seller: ShopSpell
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  • Delivery by: Jul 05 to Jul 07
  • Notes: Brand New Book. Order Now.
[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intels very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

NoC architectures are seen as a possible solution to burgeoning global wiring delays in many-core chips, and this work deals with the main issues that need to be resolved in performance, energy efficiency, reliability, variability and silicon area consumption.

[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intels very recently announced 80-core TeraFLOP chip [5lӟ
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