Pipelined ADC Design and Enhancement Techniques [Hardcover]

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Pipelined ADCs have seen phenomenal improvements in performance in recent years. This book offers a clear understanding of the design tradeoffs and state-of-the-art techniques used to implement todays high-performance, low power ADCs.

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Chapter 1: Introduction. 1.1 : Overview. 1.2 : Chapter outline. SECTION I: PIPELINED ADC DESIGN. Chapter 2: ADC Architectures. 2.1 : Overview. 2.2 : Factors which determine ADC resolution and linearity. 2.3 : ADC architectures. 2.4 : ADC Figure-of-Merit. 2.5 : Flash ADC. 2.6 : SAR ADC. 2.7 : Sub-sampling. 2.8 : Summary. Chapter 3: Pipelined ADC Architecture Overview. 3.1 : Overview. 3.2 : Pipelined ADC introduction. 3.3 : Multiplying Digital to Analog Converter (MDAC). 3.4 : Opamp DC gain requirements. 3.5 : Opamp bandwidth requirements. 3.6 : Thermal noise requirements. 3.7 : MDAC design - capacitor matching/linearity. 3.8 : Error correction in Pipelined ADCs  relaxed sub-ADC requirements. 3.9 : Sub-ADC design  comparator. 3.10 : Front-end Sample-and-hold. 3.11 : Summary. Chapter 4: Scaling Power with Sampling rate in an ADC. 4.1 : Overview. 4.2 : ADC power as a function of sampling rate. 4.3 : Digital versus analog power. 4.4 : Weak inversion model  EKV. 4.5 : Weak inversion issues  mismatch. 4.6 : Current scaling: Multiple design corners. 4.7 : Current scaling  Bias point sensitivity. 4.8 : Current scaling  IR drops. 4.9 : Summary. Cl“g