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A Roadmap for Formal Property Verification [Paperback]

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  • Category: Books (Computers)
  • Author:  Dasgupta, Pallab
  • Author:  Dasgupta, Pallab
  • ISBN-10:  9048171857
  • ISBN-10:  9048171857
  • ISBN-13:  9789048171859
  • ISBN-13:  9789048171859
  • Publisher:  Springer
  • Publisher:  Springer
  • Binding:  Paperback
  • Binding:  Paperback
  • Pub Date:  01-Feb-2010
  • Pub Date:  01-Feb-2010
  • SKU:  9048171857-11-SPRI
  • SKU:  9048171857-11-SPRI
  • Item ID: 100946420
  • List Price: $109.99
  • Seller: ShopSpell
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  • Delivery by: Jul 07 to Jul 09
  • Notes: Brand New Book. Order Now.

Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification  a roadmap that shows how to glue FPV technology into the traditional validation flow. The book explores the key issues in this powerful technology through simple examples that mostly require no background on formal methods.

Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification  a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples  you do not need any background on formal methods to read most parts of this book.

1. Introduction. 1.1. Writing our First Formal Specification. 1.2. Is my specification correct? 1.3. Have I written enough properties? 1.4. Property Verification. 1.5. Verification by Specification Refinement. 1.6. The new flow. 2. Languages for Temporal Properties. 2.1. The basic temporal operators. 2.2. Logics for temporal specification. 2.3. System Verilog Assertions. 2.4. Architectural Styles for Assertion IPs. 2.5. Concluding Remarks. 2.6. Bibliographic Notes. 3. How does the property checker work? 3.1. Checkers are state machines! 3.2. The verification strategy. 3.3. Dynamic property verification. 3.4. Formal property verification. 3.5. BDD-based Formal Property Verification. 3.6. SAT-based Formal Property Verification. 3.7. Concluding Remarks. 3.8. Bibliographic Notes. 4. Is my specification consistent? 4.1. l“{
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