Testing of Interposer-Based 2.5D Integrated Circuits [Hardcover]

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits.  The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies.  This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.

Introduction.- Pre-Bond Testing of the Silicon Interposer.- Post-Bond Scan-based Testing of Interposer Interconnects.- Test Architecture and Test-Path Scheduling.- Built-In Self-Test.- ExTest Scheduling and Optimization.- A Programmable Method for Low-Power Scan Shift in SoC Dies.- Conclusions.-

Ran Wang is a Senior DFT Engineer at NVIDIA in Santa Clara, CA. Dr. Wang received the B. Sci. degree from Zhejiang University, Hangzhou, China, in 2012, and the M.S.E and Ph.D degree from the Department of Electrical and Computer Engineering, Duke University in 2014 and 2016. His current research interests include testing and design-for-testability of 2.5D ICs and 3D ICs.

Krishnendu Chakrabarty is the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering at Duke University in Durham, NC.  He has been at Duke University since 1998. His current research is focused on: testing and design-for-testability of integrated circuits (especially 3D and multicore chips); digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure. Hisló`