Timing Performance of Nanometer Digital Circuits Under Process Variations [Hardcover]

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations.  Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications.  Various circuit-level design hints are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

Introduction.- Mathematical Fundamentals.- Process Variations.- Gate delay under process variations.- Path Delay Under Process Variations.- Circuit Analysis under Process Variations.- FinFET Technology and design issues.

Victor Champac received the Electrical Engineering Degree in 1987 from the Autonomous University of Nuevo Leon, Mexico. He received the Ph.D. degree in 1993 from the Polytechnic University of Catalonia (UPC), Spain. From 1988 to 1993 he was Associate Professor at the Electronic Engineering Department of the UPC. In 1993 he joined the National Institute for Astrophysics, Optics and Electronics (INAOE) in Mexico where he is Titular Professor. He made sabbatical in 2001-2002 at Motorola and in 2010-2011 at the University of California (UCSD). Dr. Champac was a co-founder of the Test Technology Technical Council-Latin America of IEEE Computer Society.  He was co-General Chair of the 2nd, 9th, 13th and 16th IEEE Latilã'