Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits [Hardcover]

Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted on the fly by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.This book provides theoretical and practical background on the implementation of in-situ delay monitors. It details dynamic and adaptive voltage scaling techniques as well as the impact of variations at shrinking technology nodes.

1 Introduction.

2 Sources of Variation. 2.1 Process Variations. 2.2 Voltage Variations. 2.3 Temperature Variations. 2.4 Aging. 2.5 Summary.

3 Related Work. 3.1 Dynamic Voltage Scaling. 3.2 Adaptive Voltage Scaling.

4 Adaptive Voltage Scaling by In-situ Delay Monitoring. 4.1 Principle of Operation. 4.2 Overall AVS Control Loop.

5 Design of In-situ Delay Monitors. 5.1 Delay-element based Pre-Error Flip-Flop. 5.2 Duty-Cycle based Pre-Error Flip-Flops. 5.3 Comparison of In-situ Delay Monitors.

6 Modeling the AVS Control Loop. 6.1 Simulation Methodology. 6.2 Markov Model of the lS±